Jonathan Xue

Jonathan Xue is a Computer Engineering student at the University of California, Los Angeles (UCLA). This is the personal website and portfolio of Jonathan Xue — projects, research, experience, and contact.

About Jonathan Xue

Jonathan Xue (jxue, jxue235) studies B.S. Computer Engineering at UCLA's Henry Samueli School of Engineering and is in the ECE Honors Program · Fast Track. Jonathan's interests include digital systems, FPGA design, high-level synthesis (HLS) compilers, computer architecture, and efficient LLM inference on edge devices. Jonathan is based in Los Angeles, California.

Research and Experience

Undergraduate Researcher — UCLA VAST Lab (May 2025 — Present). Co-author on a PACT 2026 submission on an xDSL-based compiler for cycle-critical streaming accelerators in HLS, with FFT as the case study. Beat leading RTL FFT libraries (Xilinx LogiCORE) on latency at similar resource utilization. Designed bank-conflict-free memory layouts for any linear permutation using the F₂ space. Fine-tuning a small model to advise general-purpose LLMs on HLS pragma tuning and hardware-design decisions.
Software Intern — OuterProduct Labs (May 2026 — Present). Benchmarking OuterProduct across datasets including time-series data, training a transformer on a time-series dataset and distilling it onto OuterProduct.

Projects by Jonathan Xue

snapdragon-8-elite-llm-optimization (2025) — Llama 3.2 1B Instruct with Hierarchical Memory Transformer + AWQ weight scaling on Snapdragon 8 Elite. SFT + DPO on LFM2-1.2B. Placed 3rd of 20 teams on throughput · accuracy · power. C++, llama.cpp.
pipelined-out-of-order-riscv-processor (2025) — 2-issue out-of-order RISC-V RV32I core with a 7-stage pipeline and branch prediction, synthesized on an Arty A7-100T FPGA. SystemVerilog, Vivado.
fpga-digital-audio-visualizer (2025) — Real-time audio visualizer on an Altera MAX10 FPGA. Radix-2 64-point fully-streaming DIT FFT splits microphone input into frequency bins; double-buffered VGA controller prevents screen tearing. SystemVerilog, Quartus.

Skills

Languages: C, C++, Java, Python, SystemVerilog, Verilog, CUDA, Vitis HLS, OpenMP, TCL. Hardware: Quartus, Questa, Vivado, Vitis, Logisim, LTSpice. ML / DSL: xDSL, MLIR, AG2, Llama Factory, llama.cpp. Systems: Linux, UNIX, Git, Spring Boot.

Honors and Awards

ECE Honors Program · Fast Track
Eta Kappa Nu (HKN) Member
MathWorks M3 Challenge Finalist 2024 — $5,000
AIME 4x Qualifier
CyberPatriot · 5th Place