Jonathan Xue

UCLA Computer Engineering student

Projects

  • Designed and verified an audio visualizer on an Altera MAX10 FPGA using SystemVerilog.
  • Implemented a radix-2 64-point DIT FFT to filter sound into frequency bins from an analog microphone.
  • Displayed the frequency bins using a double-buffered VGA controller to prevent screen tearing.
  • Designed and verified a RISC-V 32I (base integer instructions) processor running on an Arty A7-100T FPGA using Verilog.

Contact

Email: [email protected]
GitHub: github.com/jonathanxue235
LinkedIn: linkedin.com/in/jxue235